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DC Field | Value | Language |
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dc.contributor.author | Bhuyan, Muhibul Haque | - |
dc.date.accessioned | 2022-08-21T10:13:15Z | - |
dc.date.available | 2022-08-21T10:13:15Z | - |
dc.date.issued | 2007-12-31 | - |
dc.identifier.citation | M. H. Bhuyan, “Finite State Machine Based Directional Counter Design Using VHDL,” Journal of Bangladesh Electronics Society, ISSN: p-1816-1510, vol. 7, no 1-2, pp. 45-53, June-Dec. 2007. | en_US |
dc.identifier.issn | p-1816-1510 | - |
dc.identifier.uri | http://dspace.aiub.edu:8080/jspui/handle/123456789/682 | - |
dc.description | This is individual research work. | en_US |
dc.description.abstract | In this work, a directional counter circuit is designed using a light source and light sensor, up-down counter, timer, and a logic circuit to sense the direction of movement of objects and to count the number of objects passing through a gate. A finite-state machine-based approach is adopted for this design. Each step of the design is described with a state diagram, state table, state-assigned table, 'K-maps', Boolean expressions, and logic circuit diagram. Finally, the logic circuit was simulated in VHDL for different test patterns to verify the designed circuit. It is found that the circuit works properly for all conditions. | en_US |
dc.description.sponsorship | Self-funded. | en_US |
dc.language.iso | en_US | en_US |
dc.publisher | Bangladesh Electronics and Informatics Society | en_US |
dc.subject | Finite State Machine | en_US |
dc.subject | Directional Counter | en_US |
dc.subject | FPGA | en_US |
dc.subject | Simulation | en_US |
dc.subject | VHDL | en_US |
dc.subject | Logic Circuit Design | en_US |
dc.title | Finite State Machine Based Directional Counter Design Using VHDL | en_US |
dc.type | Article | en_US |
Appears in Collections: | Publications From Faculty of Engineering |
Files in This Item:
File | Description | Size | Format | |
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Draft_DSpace_Publication_Info_Upload_FE_Prof Muhibul BEISJ FSM.docx | 2.93 MB | Microsoft Word XML | View/Open |
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