Please use this identifier to cite or link to this item: http://dspace.aiub.edu:8080/jspui/handle/123456789/711
Full metadata record
DC FieldValueLanguage
dc.contributor.authorBhuyan, Muhibul Haque-
dc.contributor.authorKhosru, Quazi Deen Mohd-
dc.date.accessioned2022-08-21T11:10:54Z-
dc.date.available2022-08-21T11:10:54Z-
dc.date.issued2017-04-27-
dc.identifier.citationM. H. Bhuyan and Q. D. M. Khosru, “Linear Asymmetric Pocket Profile Based Pinch Off Voltage Model for Nano Scale n-MOSFET,” Proceedings of the IEEE sponsored International Conference on Electrical, Computer and Communication Engineering (ICECCE2017), organized by the Chittagong University of Engineering and Technology (CUET), Cox’s Bazar, Bangladesh, 16-18 Feb. 2017, pp. 28-32.en_US
dc.identifier.otherINSPEC: 16851138-
dc.identifier.urihttp://dspace.aiub.edu:8080/jspui/handle/123456789/711-
dc.description.abstractThis work reports on developing an analytical pinch-off voltage model for the pocket implanted nano scale n-MOSFETs based on an asymmetric linear pocket profile at the source side under the gate of the device. Straight line approximated equation is used to simulate the pocket profile from the source towards the drain along the gate length at the surface of the MOS device. The effective doping concentration is derived for the whole gate length and is incorporated in the pinch-off voltage model that is obtained from the strong inversion charge expression at the surface. Then the pinch-off voltage is simulated for various drain and gate biases as well as for various device parameters. To observe the model validity, inversion charge profile, surface potential at various points along the channel, drain current vs. drain voltage curve is plotted for various gate biases by incorporating this effective channel doping concentration as well as the developed pinch-off voltage model. The simulation results show that the developed pinch-off voltage model can be used to study, simulate and characterize the pocket implanted ULSI devices.en_US
dc.description.sponsorshipSelf-fundeden_US
dc.language.isoen_USen_US
dc.publisherIEEEen_US
dc.subjectPocket implanted MOS deviceen_US
dc.subjectnano scaled n-MOSFETen_US
dc.subjectPinch-off voltage modelen_US
dc.subjectAsymmetric pocket profileen_US
dc.subjectPeak pocket concentrationnen_US
dc.subjectPocket lengthen_US
dc.titleLinear Asymmetric Pocket Profile Based Pinch Off Voltage Model for Nano Scale n-MOSFETen_US
dc.typeArticleen_US
Appears in Collections:Publications From Faculty of Engineering

Files in This Item:
File Description SizeFormat 
Draft_DSpace_Publication_Info_Upload_FE_Prof Muhibul IEEE-ECCE Asym Vp.docx3.33 MBMicrosoft Word XMLView/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.