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DC Field | Value | Language |
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dc.contributor.author | Bhuyan, Muhibul Haque | - |
dc.contributor.author | Khosru, Quazi Deen Mohd | - |
dc.date.accessioned | 2022-08-21T11:10:54Z | - |
dc.date.available | 2022-08-21T11:10:54Z | - |
dc.date.issued | 2017-04-27 | - |
dc.identifier.citation | M. H. Bhuyan and Q. D. M. Khosru, “Linear Asymmetric Pocket Profile Based Pinch Off Voltage Model for Nano Scale n-MOSFET,” Proceedings of the IEEE sponsored International Conference on Electrical, Computer and Communication Engineering (ICECCE2017), organized by the Chittagong University of Engineering and Technology (CUET), Cox’s Bazar, Bangladesh, 16-18 Feb. 2017, pp. 28-32. | en_US |
dc.identifier.other | INSPEC: 16851138 | - |
dc.identifier.uri | http://dspace.aiub.edu:8080/jspui/handle/123456789/711 | - |
dc.description.abstract | This work reports on developing an analytical pinch-off voltage model for the pocket implanted nano scale n-MOSFETs based on an asymmetric linear pocket profile at the source side under the gate of the device. Straight line approximated equation is used to simulate the pocket profile from the source towards the drain along the gate length at the surface of the MOS device. The effective doping concentration is derived for the whole gate length and is incorporated in the pinch-off voltage model that is obtained from the strong inversion charge expression at the surface. Then the pinch-off voltage is simulated for various drain and gate biases as well as for various device parameters. To observe the model validity, inversion charge profile, surface potential at various points along the channel, drain current vs. drain voltage curve is plotted for various gate biases by incorporating this effective channel doping concentration as well as the developed pinch-off voltage model. The simulation results show that the developed pinch-off voltage model can be used to study, simulate and characterize the pocket implanted ULSI devices. | en_US |
dc.description.sponsorship | Self-funded | en_US |
dc.language.iso | en_US | en_US |
dc.publisher | IEEE | en_US |
dc.subject | Pocket implanted MOS device | en_US |
dc.subject | nano scaled n-MOSFET | en_US |
dc.subject | Pinch-off voltage model | en_US |
dc.subject | Asymmetric pocket profile | en_US |
dc.subject | Peak pocket concentrationn | en_US |
dc.subject | Pocket length | en_US |
dc.title | Linear Asymmetric Pocket Profile Based Pinch Off Voltage Model for Nano Scale n-MOSFET | en_US |
dc.type | Article | en_US |
Appears in Collections: | Publications From Faculty of Engineering |
Files in This Item:
File | Description | Size | Format | |
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Draft_DSpace_Publication_Info_Upload_FE_Prof Muhibul IEEE-ECCE Asym Vp.docx | 3.33 MB | Microsoft Word XML | View/Open |
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