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dc.contributor.authorJameel, Kazi Muhammad-
dc.contributor.authorMannan, Mohammad Abdul-
dc.contributor.authorHasan, Md. Tanvir-
dc.date.accessioned2024-01-16T10:41:20Z-
dc.date.available2024-01-16T10:41:20Z-
dc.date.issued2016-
dc.identifier.citationKazi Muhammad Jameel, Mohammad Abdul Mannan, Md. Tanvir Hasan, “Design of a Multipurpose Ternary Arithmetic Circuit Using CNTFET”, Journal of Semiconductor Devices and Circuits (STM Journals), Vol. 3, Issue 1, pp. 13-24, 2016.en_US
dc.identifier.issn2455-3379-
dc.identifier.urihttp://dspace.aiub.edu:8080/jspui/handle/123456789/2057-
dc.description.abstractIn this paper, a multipurpose ternary arithmetic circuit is presented for ternary processors based on carbon nanotube field effect transistors (CNTFETs). Both addition and subtraction can be performed using same circuit’s configuration, which is the special feature of the proposed circuit. The combination of pseudo and complimentary logic structure are employed to blend the binary and ternary logic techniques. The propagation delay and power delay product are 139.5 pico second and 3.18 femto Joule, which indicates significant improvement in power consumption, delay and PDP, compared to few recent ternary full adder designs.en_US
dc.language.isoenen_US
dc.publisherSTM Journals, an imprint of CELNET (Consortium e-Learning Network Pvt. Ltd.)en_US
dc.subjectTernary arithmetic circuitsen_US
dc.subjectternary full adderen_US
dc.subjectTFAen_US
dc.subjectternary full subtractoren_US
dc.subjectTFSen_US
dc.titleDesign of a Multipurpose Ternary Arithmetic Circuit Using CNTFETen_US
dc.typeArticleen_US
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