Design and Implementation of FPGA based 32-bit Carry Look Ahead Adder using Verilog HDL in Xilinx Environment

Bhuyan, Muhibul Haque; Nabi, Raisa Afshah

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DC Field	Value	Language
dc.contributor.author	Bhuyan, Muhibul Haque	-
dc.contributor.author	Nabi, Raisa Afshah	-
dc.date.accessioned	2022-08-21T10:12:15Z	-
dc.date.available	2022-08-21T10:12:15Z	-
dc.date.issued	2009-12-31	-
dc.identifier.citation	M. H. Bhuyan and R. A. Nabi “Design and Implementation of FPGA based 32-bit Carry Look Ahead Adder using Verilog HDL in Xilinx Environment,” Journal of Bangladesh Electronics Society, ISSN: p-1816-1510, vol. 9, no 1-2, pp. 161-167, June-December 2009.	en_US
dc.identifier.issn	p-1816-1510	-
dc.identifier.uri	http://dspace.aiub.edu:8080/jspui/handle/123456789/680	-
dc.description	This is joint research work.	en_US
dc.description.abstract	This paper presents the design method and simulation strategy of a 32-bit carry look ahead adder using verilog HDL. To implement this large adder,2-bil and 4-bit adder blocks are used separately. The carry signals are generated using the logic equations in verilog HDL. The verilog HDL design is verified using ModelSim simulator in Xilinx environment for various test inputs. The simulation results are then presented.	en_US
dc.description.sponsorship	Self-funded	en_US
dc.language.iso	en_US	en_US
dc.publisher	Bangladesh Electronics and Informatics Society	en_US
dc.relation.ispartofseries	;15	-
dc.subject	32-bit carry look ahead adder	en_US
dc.subject	verilog	en_US
dc.subject	verilog HDL design	en_US
dc.subject	ModelSim simulator	en_US
dc.subject	FPGA	en_US
dc.subject	Xilinx environment	en_US
dc.title	Design and Implementation of FPGA based 32-bit Carry Look Ahead Adder using Verilog HDL in Xilinx Environment	en_US
dc.type	Article	en_US
Appears in Collections:	Publications From Faculty of Engineering

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