Linear Asymmetric Pocket Profile Based Low Frequency Drain Current Flicker Noise Model for Pocket Implanted Nano Scale n-MOSFET

Abstract

This paper presents an analytical drain current flicker noise model for the asymmetric pocket implanted nano scale n-MOSFET. The model is developed by assuming asymmetric linear pocket doping profile at the source edge only. The number of channel charges is found for the two regions and are incorporated in the unified flicker noise model developed by Hung et al. for the conventional metal oxide semiconductor field effect transistor (MOSFET). Simulation results for the various device as well as pocket profile parameters show that the derived drain current flicker noise model has a simple compact form that can be utilized to study and characterize the pocket implanted advanced ULSI devices.