1. American International University-Bangladesh
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Please use this identifier to cite or link to this item: http://dspace.aiub.edu:8080/jspui/handle/123456789/792
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dc.contributor.authorBhuyan, Muhibul Haque-
dc.contributor.authorKhosru, Quazi Deen Mohd-
dc.date.accessioned2022-08-30T10:27:00Z-
dc.date.available2022-08-30T10:27:00Z-
dc.date.issued2012-10-02-
dc.identifier.citationM. H. Bhuyan and Q. D. M. Khosru, “Analytical Threshold Voltage Model for Pocket Implanted Fully Depleted Thin Film SOI n-MOSFET,” Proceedings of the National Conference on Electronics and ICT for National Development organized by the Bangladesh Electronics Society, Dhaka, 3-4 October 2012, pp. 238-242.en_US
dc.identifier.urihttp://dspace.aiub.edu:8080/jspui/handle/123456789/792-
dc.description.abstractIn this paper, a modified structure of the fully depleted thin film SOI n-MOSFET has been proposed by implanting symmetric pockets both at the source and drain sides. Then an analytical threshold voltage model for this proposed structure has been presented. The model has been simulated in a MATLAB environment for different pocket profile parameters and device dimensions. Simulation results reveal that the incorporation of pockets in the thin film SOI n-MOSFET can suppress the short channel effects significantly.en_US
dc.description.sponsorshipSelf-fundeden_US
dc.language.isoenen_US
dc.publisherBangladesh Electronics and Informatics Societyen_US
dc.subjectPocket implanted MOS deviceen_US
dc.subjectSOI-MOSFETen_US
dc.subjectThreshold Volageen_US
dc.subjectDrain Voltageen_US
dc.subjectGate Voltageen_US
dc.subjectPocket lengthen_US
dc.subjectPocket concentrationen_US
dc.subjectThin Filmen_US
dc.subjectMATLABen_US
dc.subjectSimulationen_US
dc.subjectSCEen_US
dc.subjectRSCEen_US
dc.titleAnalytical Threshold Voltage Model for Pocket Implanted Fully Depleted Thin Film SOI n-MOSFETen_US
dc.typeArticleen_US
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