Please use this identifier to cite or link to this item: http://dspace.aiub.edu:8080/jspui/handle/123456789/521
Title: Design, Simulation, and Analysis of Different Operational Factors of a 4-bit Carry Look-Ahead Adder Circuit in Microwind at Several CMOS Technology Nodes
Authors: Bhuyan, Muhibul Haque
Akhtaruzzaman, Md.
Keywords: CMOS
Carry Look Ahead (CLA)
Full Adder
VLSI
Technology Node
Power Consumption
Area
Noise
Propagation Delay
Simulation
Issue Date: 31-Oct-2021
Publisher: IOSR
Citation: M. H. Bhuyan and M. Akhtaruzzaman, “Design, Simulation, and Analysis of Different Operational Factors of a 4-bit Carry Look-Ahead Adder Circuit in Microwind at Several CMOS Technology Nodes,” IOSR Journal of VLSI and Signal Processing (IOSR-JVSP), IF=2.82, ISSN: e-2319-4200, p-2319-4197, vol. 11, issue 5, September-October 2021, pp. 1-10.
Abstract: In Very Large Scale Integration (VLSI) technology, the main objective is to shrink the area and thereby to raise the packing density for performance improvement in terms of power consumption, noise, delay, operating frequency, etc. A carry look-ahead adder circuit is an important block in any digital circuit. It improves the parallel addition process. Since the number of bits in various digital circuits is being increased, as such, we need millions of transistors to perform several functions in parallel. But it increases the need for surface area, power consumption, noise, and other factors. Therefore, we need to reduce the transistor size to alleviate these problems. In this research article, we designed a 4-bit carry look ahead full adder circuit at several technology nodes using Proteus and then simulated it in Microwind. The designed circuit and layout are presented here. Besides, various operational factors are obtained to observe the benefits of the transistors’ size decrement. The layouts are converted and simulated at130 nm, 90nm, 65nm, and45nm CMOS technology nodes. From the comparative analysis, we observed that the reduction of the CMOS technology nodes increases the performance factors of the designed carry look-ahead adder circuit.
Description: This is based on a student research paper.
URI: http://dspace.aiub.edu:8080/jspui/handle/123456789/521
ISSN: e-2319-4200, p-2319-4197
Appears in Collections:Publications From Faculty of Engineering

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