Low Frequency Drain Current Flicker Noise Model for Pocket Implanted Nano Scale n-MOSFET

Abstract

This paper presents an analytical drain current flicker noise model for pocket implanted nano scale n-MOSFET. The model is developed by using two linear pocket profiles at the source and drain edges. Thus the channel is divided into three regions at source, drain and central part of the channel region. Then the number of channel charges are found for these three regions and are incorporated it in the unified flicker noise model developed by Hung et al. for the conventional metal oxide semiconductor field effect transistor. The simulation results show that the derived drain current flicker noise model has a simple compact form.