A Threshold Voltage Model for sub-100 nm Pocket Implanted NMOSFET

Bhuyan, Muhibul Haque; Ferdous, Fouzia; Khosru, Quazi Deen Mohd

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DC Field	Value	Language
dc.contributor.author	Bhuyan, Muhibul Haque	-
dc.contributor.author	Ferdous, Fouzia	-
dc.contributor.author	Khosru, Quazi Deen Mohd	-
dc.date.accessioned	2022-08-22T05:06:13Z	-
dc.date.available	2022-08-22T05:06:13Z	-
dc.date.issued	2007-05-07	-
dc.identifier.citation	M. H. Bhuyan, F. Ferdous, and Q. D. M. Khosru, “A Threshold Voltage Model for sub-100 nm Pocket Implanted NMOSFET,” Proceedings of the International Conference on Electrical and Computer Engineering, Dhaka, 19-21 December 2006, pp. 522-525.	en_US
dc.identifier.uri	http://dspace.aiub.edu:8080/jspui/handle/123456789/725	-
dc.description	Work as part of PhD thesis	en_US
dc.description.abstract	Pocket implantation is a very useful technique to suppress short channel effects in submicrometer MOS devices. This paper presents a threshold voltage model of pocket implanted sub-100 nm nMOSFETs. The proposed model is derived using two linear equations to simulate the pockets along the channel at the surface from the source and drain edges towards the center of the MOSFET. The threshold voltage equation is obtained by solving the 1D Poisson's equation and then applying Gauss's law at the surface. The model has a simple compact form that can be utilized to study and characterize the pocket implanted advanced ULSI devices.	en_US
dc.description.sponsorship	Self	en_US
dc.language.iso	en_US	en_US
dc.publisher	IEEE	en_US
dc.subject	Pocket implanted MOS device	en_US
dc.subject	nano scaled n-MOSFET	en_US
dc.subject	Surface potential	en_US
dc.subject	Drain Voltage	en_US
dc.subject	Gate Voltage	en_US
dc.subject	Pocket length	en_US
dc.subject	Pocket concentration	en_US
dc.subject	Threshold voltage	en_US
dc.title	A Threshold Voltage Model for sub-100 nm Pocket Implanted NMOSFET	en_US
dc.type	Article	en_US
Appears in Collections:	Publications From Faculty of Engineering

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