Please use this identifier to cite or link to this item: http://dspace.aiub.edu:8080/jspui/handle/123456789/1937
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dc.contributor.authorShohail, Kamrul Islam-
dc.contributor.authorAwsaf, Wajiha-
dc.contributor.authorSayel, Saniat Uddin-
dc.contributor.authorNitu, Mahabuba Khanam-
dc.contributor.authorBhuyan, Muhibul Haque-
dc.date.accessioned2023-12-13T06:14:18Z-
dc.date.available2023-12-13T06:14:18Z-
dc.date.issued2023-11-01-
dc.identifier.citationKamrul Islam Shohail, Wajiha Awsaf, Saniat Uddin Sayel, Mahabuba Khanam Nitu, and Muhibul Haque Bhuyan, “Design Process, Simulation, and Analysis of a Common Source MOS Amplifier Circuit in Cadence at 45 nm CMOS Technology Node,” IOSR Journal of VLSI and Signal Processing (IOSR-JVSP), IF=2.82, ISSN: e-2319-4200, p-2319-4197, vol. 13, issue 6, series-I, November - December 2023, pp. 1-14.en_US
dc.identifier.issne-ISSN: 2319-4200, p-ISSN: 2319-4197-
dc.identifier.urihttp://dspace.aiub.edu:8080/jspui/handle/123456789/1937-
dc.descriptionIt is based on a VLSI course project.en_US
dc.description.abstractThis paper presents the design and analysis of a 1-bit Arithmetic Logic Unit (ALU) with and without a full adder circuit. The objective of the study is to compare the outputs of the two designs considering the performance factors of delay, power, and surface area. The designs were implemented using Cadence Virtuoso and simulated using a 90 nm CMOS process technology. As such, the circuit is built from two paired MOS transistors (i.e., using both N- and P-type MOSs in the pull-down and pull-up circuits, respectively) having a 90 nm gate length. The gate widths are selected as 1 and 2 m, respectively. Transistors are nominated from the general design CMOS process kit at 90 nm technology node, i.e. gpdk090 library of the Cadence. DC, transient, and noise analyses were performed with a 3.8 V DC power supply to characterize the behavior of the circuits. The results indicate that the ALU without the full adder has lower delay and power consumption but a larger area, while the ALU with the full adder has higher delay and power consumption but a smaller area. The findings of this study can provide insights for designers to choose the appropriate ALU design based on their specific requirements and provide a confidence boost before going into the fabrication steps.en_US
dc.description.sponsorshipSelf-fundeden_US
dc.language.isoen_USen_US
dc.publisherIOSR Journals, Indiaen_US
dc.relation.ispartofseries;1-
dc.subjectCMOSen_US
dc.subjectCadenceen_US
dc.subjectVLSIen_US
dc.subjectALUen_US
dc.subjectLogic Gatesen_US
dc.subjectFull Adderen_US
dc.subject90 nm CMOS Nodeen_US
dc.subjectPerformanceen_US
dc.titleDesign Steps, Simulation, and Analysis of a 1-bit ALU in Cadence at 90 nm CMOS Nodeen_US
dc.typeArticleen_US
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