Design and Implementation of FPGA based 32-bit Carry Look Ahead Adder using Verilog HDL in Xilinx Environment

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Title:	Design and Implementation of FPGA based 32-bit Carry Look Ahead Adder using Verilog HDL in Xilinx Environment
Authors:	Bhuyan, Muhibul Haque Nabi, Raisa Afshah
Keywords:	32-bit carry look ahead adder verilog verilog HDL design ModelSim simulator FPGA Xilinx environment
Issue Date:	31-Dec-2009
Publisher:	Bangladesh Electronics and Informatics Society
Citation:	M. H. Bhuyan and R. A. Nabi “Design and Implementation of FPGA based 32-bit Carry Look Ahead Adder using Verilog HDL in Xilinx Environment,” Journal of Bangladesh Electronics Society, ISSN: p-1816-1510, vol. 9, no 1-2, pp. 161-167, June-December 2009.
Series/Report no.:	;15
Abstract:	This paper presents the design method and simulation strategy of a 32-bit carry look ahead adder using verilog HDL. To implement this large adder,2-bil and 4-bit adder blocks are used separately. The carry signals are generated using the logic equations in verilog HDL. The verilog HDL design is verified using ModelSim simulator in Xilinx environment for various test inputs. The simulation results are then presented.
Description:	This is joint research work.
URI:	http://dspace.aiub.edu:8080/jspui/handle/123456789/680
ISSN:	p-1816-1510
Appears in Collections:	Publications From Faculty of Engineering

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