Please use this identifier to cite or link to this item: http://dspace.aiub.edu:8080/jspui/handle/123456789/682
Title: Finite State Machine Based Directional Counter Design Using VHDL
Authors: Bhuyan, Muhibul Haque
Keywords: Finite State Machine
Directional Counter
FPGA
Simulation
VHDL
Logic Circuit Design
Issue Date: 31-Dec-2007
Publisher: Bangladesh Electronics and Informatics Society
Citation: M. H. Bhuyan, “Finite State Machine Based Directional Counter Design Using VHDL,” Journal of Bangladesh Electronics Society, ISSN: p-1816-1510, vol. 7, no 1-2, pp. 45-53, June-Dec. 2007.
Abstract: In this work, a directional counter circuit is designed using a light source and light sensor, up-down counter, timer, and a logic circuit to sense the direction of movement of objects and to count the number of objects passing through a gate. A finite-state machine-based approach is adopted for this design. Each step of the design is described with a state diagram, state table, state-assigned table, 'K-maps', Boolean expressions, and logic circuit diagram. Finally, the logic circuit was simulated in VHDL for different test patterns to verify the designed circuit. It is found that the circuit works properly for all conditions.
Description: This is individual research work.
URI: http://dspace.aiub.edu:8080/jspui/handle/123456789/682
ISSN: p-1816-1510
Appears in Collections:Publications From Faculty of Engineering

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