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Center for Nanotechnology Research
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Title
Author(s)
2014-03-27
Linear Asymmetric Pocket Profile Based Low Frequency Drain Current Flicker Noise Model for Pocket Implanted Nano Scale n-MOSFET
Bhuyan, Muhibul Haque
;
Khosru, Quazi Deen Mohd
2017-03-16
Linear Pocket Profile Based Pinch Off Voltage Model for Nano Scale n-MOSFET
Bhuyan, Muhibul Haque
;
Khosru, Quazi Deen Mohd
2017-04-27
Linear Asymmetric Pocket Profile Based Pinch Off Voltage Model for Nano Scale n-MOSFET
Bhuyan, Muhibul Haque
;
Khosru, Quazi Deen Mohd
2009-01-27
Linear Pocket Profile Based Threshold Voltage Model For Sub-100 nm n-MOSFET Incorporating Substrate and Drain Bias Effects
Bhuyan, Muhibul Haque
;
Khosru, Quazi Deen Mohd
2007-05-07
A Threshold Voltage Model for sub-100 nm Pocket Implanted NMOSFET
Bhuyan, Muhibul Haque
;
Ferdous, Fouzia
;
Khosru, Quazi Deen Mohd
2009-01-27
An Analytical Surface Potential Model for Pocket Implanted Sub-100 nm n-MOSFET
Bhuyan, Muhibul Haque
;
Khosru, Quazi Deen Mohd
2012-12-01
Linear Asymmetric Pocket Profile Based Threshold Voltage Model for Nano Scale n-MOSFET
Bhuyan, Muhibul Haque
;
Khosru, Quazi Deen Mohd
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Bhuyan, Muhibul Haque
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Ferdous, Fouzia
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Threshold voltage
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Drain Voltage
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Pocket concentration
2
Drain Bias
2
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2
Gate Voltage
2
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2
Pinch-off voltage model
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