A Threshold Voltage Model for sub-100 nm Pocket Implanted NMOSFET

Please use this identifier to cite or link to this item: http://dspace.aiub.edu:8080/jspui/handle/123456789/725

Title:	A Threshold Voltage Model for sub-100 nm Pocket Implanted NMOSFET
Authors:	Bhuyan, Muhibul Haque Ferdous, Fouzia Khosru, Quazi Deen Mohd
Keywords:	Pocket implanted MOS device nano scaled n-MOSFET Surface potential Drain Voltage Gate Voltage Pocket length Pocket concentration Threshold voltage
Issue Date:	7-May-2007
Publisher:	IEEE
Citation:	M. H. Bhuyan, F. Ferdous, and Q. D. M. Khosru, “A Threshold Voltage Model for sub-100 nm Pocket Implanted NMOSFET,” Proceedings of the International Conference on Electrical and Computer Engineering, Dhaka, 19-21 December 2006, pp. 522-525.
Abstract:	Pocket implantation is a very useful technique to suppress short channel effects in submicrometer MOS devices. This paper presents a threshold voltage model of pocket implanted sub-100 nm nMOSFETs. The proposed model is derived using two linear equations to simulate the pockets along the channel at the surface from the source and drain edges towards the center of the MOSFET. The threshold voltage equation is obtained by solving the 1D Poisson's equation and then applying Gauss's law at the surface. The model has a simple compact form that can be utilized to study and characterize the pocket implanted advanced ULSI devices.
Description:	Work as part of PhD thesis
URI:	http://dspace.aiub.edu:8080/jspui/handle/123456789/725
Appears in Collections:	Publications From Faculty of Engineering

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